Newest role found 5 days ago
Tenstorrent
49 open roles in Austin, Santa Clara and 3 more places.
- Open roles
- 49
- New this week
- 1
- Cities
- 5
- Teams
- 26
Open roles 49
- ATE Test Development EngineerAustin · Silicon: DFT and TestNew
- IP Customer Program ManagerSanta Clara · Operations: IP Ops & PMO7d
- Applied AI EngineerSanta Clara · AI SW: TPM7d
- Sr. In-House CounselBoston · Operations: Legal11d
- Datacenter & Agentic AI Workload Performance Analysis EngineerSanta Clara · Architecture: Workload12d
- Test Engineer, System-Level Test (SLT)Austin · Silicon: DFT and Test13d
- Mixed Signal IC Layout EngineerSanta Clara · Silicon: Mixed Signal Design2w
- Post-Silicon Lab ManagerSanta Clara · RISC V: PostSi2w
- Staff Engineer,Post-Silicon ValidationAustin · RISC V: PostSi2w
- RecruiterSanta Clara · Operations: Recruiting2w
- Startup LawyerSanta Clara · Operations: Legal2w
- Sr. Engineer, Performance Infrastructure (RISC-V)Santa Clara · RISC V2w
- Physical Design Engineer, TimingAustin · Advanced Physical Design: PD3w
- Performance Architect, CPU ClusterAustin · Architecture: Performance Model3w
- Corporate ControllerAustin · Operations: Finance4w
- Physical Design CPU Methodology EngineerSanta Clara · Architecture4w
- Sr. Staff Engineer, CPU (Front-End) VerificationAustin · RISC V: DV5w
- Sales Director, AI CloudSanta Clara · Experience: GTM7w
- Director, Finance SystemsAustin · Operations: Finance8w
- Staff Compensation AnalystAustin · Operations: Human Resources8w
- Staff Product Manager, PlatformSanta Clara · Systems Engineering: Product2mo
- Manager, Strategy and SolutionsAustin · Experience: GTM2mo
- Director, Strategy & SolutionsAustin · Experience: GTM2mo
- DFT EngineerSanta Clara · Architecture3mo
- Performance Modeling ArchitectAustin · Architecture: Performance Model3mo
- Technical Program ManagerAustin · Leadership: Program Management and Execution4mo
- CPU Verification Fellow, RISC-V High-Performance ProcessorAustin · Architecture: Design Verification4mo
- Sr. Staff Engineer, RTL Physical Implementation LeadAustin · RISC V: RTL4mo
- CPU Core Design Verification Testbench LeadAustin · RISC V4mo
- CPU Core Design Verification Test Generator LeadFort Collins · RISC V5mo
- Physical Design Engineer, PnRAustin · Advanced Physical Design5mo
- Full-Chip Physical Design Verification EngineerAustin · Advanced Physical Design5mo
- Physical Design EngineerAustin · Silicon: Physical Design5mo
- Top Level Physical Design EngineerAustin · Advanced Physical Design6mo
- AI/ML Physical Design Flow EngineerAustin · Advanced Physical Design6mo
- Technical Program Manager, ArchitectureSanta Clara · Architecture: TPM6mo
- Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)Santa Clara · Silicon: Mixed Signal Design7mo
- Interconnect and Compute ArchitectSanta Clara · Architecture7mo
- RISC-V AI / HPC & Agentic Software Engineering LeadSanta Clara · Architecture7mo
- Chiplet Physical Design EngineerSanta Clara · Architecture8mo
- Staff Software Engineer, Cloud InfrastructureSanta Clara · AI SW: Cloud Platform9mo
- Sales Director, Financial ServicesSanta Clara · Experience: GTM10mo
- Engineering Program Manager, RISCVAustin · RISC V11mo
- Fabric SOC ArchitectSanta Clara · Architecture13mo
- Sr. Engineer, SoC Design VerificationAustin · SoC13mo
- Technical Program Manager, Product SoftwareAustin · AI SW: TPM14mo
- Physical Design Engineer - STAAustin · Advanced Physical Design15mo
- Physical Design Engineer - PnRAustin · Advanced Physical Design2y
- Software Engineer, Acceleration Kernel DevelopmentSanta Clara · AI SW2y
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